The present invention relates to a nonvolatile semiconductor memory particularly used as a NOR-type flash EEPROM.
A NOR-type flash EEPROM has three basic modes, i.e., a program mode, an erase mode and a read mode. In the program mode, for example, operation for raising the threshold voltage of a memory cell up to not less than a predetermined value (e.g., 5.5V) is carried out. In the erase mode, operation for setting the threshold voltage of a memory cell to fall within a predetermined range (e.g., 0.5 to 3.0V) is carried out.
In case of a NOR-type flash EEPROM having an auto-program function and an auto-erase function, in the program mode, for example, it is verified whether or not the threshold voltage of a memory cell is not less than 5.5V and reprogram (rewrite) is automatically carried out until the threshold voltage of the memory cell becomes not less than 5.5V. In the erase mode, it is verified whether or not the threshold voltage of a memory cell is within a range of 0.5 to 3.0V and predetermined operation is carried out automatically until the threshold voltage of the memory cell falls within the predetermined range.
FIG. 1 shows the important parts of a conventional NOR-type flash EEPROM.
A memory cell array 11 consists of a plurality of blocks. Each block has a plurality of memory cells connected between word lines (input side) and bit lines (output side) to form a NOR relationship.
External addresses A1 to A17 are input to a multiplexer 13 either directly or through an address register 12. An address counter 16 generates internal addresses. The multiplexer 13 feeds either an external address or an internal address to a row decoder 14 and a column decoder 15.
Input data is fed to a data input register 18 and a command register 19 through an input/output buffer 17. The data of the data input register 18 is supplied to memory cells through a column selecting circuit 20.
The command register 19 recognizes a command consisting of an address and a data and outputs a control signal to the address register 12, the multiplexer 13, the data input register 18 and a control circuit 21 in response to the command.
The control circuit 21 recognizes an operation mode to be executed next based on the control signal output from the command register 19.
A potential generating circuit 22 generates various potentials corresponding to operation modes. The potential generated by the potential generating circuit 22 is applied to the control gates and the bit lines of the memory cells in each operation mode.
A verify circuit 23 verifies whether or not data program or data erase is surely carried out to a selected memory cell and outputs a result, i.e., VERIOK to the control circuit 21.
A final address detecting circuit 24 outputs a detection signal AEND indicating whether or not the final address of each block of the memory cell array 11 is detected and outputs a detection signal BEND indicating whether or not the final block of the memory cell array 11 is detected.
A timer 25 counts the number of program operations or the number of erase operations conducted to the selected memory cell. The timer 25 outputs a time out signal TIME OUT to the control circuit 21 when the number of program operations or that of erase operations conducted to the selected memory cell reaches a predetermined number.
A clock generating signal 26 generates a clock for controlling the internal operation of the flash EEPROM based on a write enable signal {overscore (WE)}, a chip enable signal {overscore (CE)}, an output enable signal {overscore (OE)} and the like.
FIG. 2 shows the memory cell array of the NOR-type flash EEPROM shown in FIG. 1. FIGS. 3 to 5 show the device structure of a portion enclosed by a broken line X in FIG. 2.
In this example, memory cells are formed in a twin well, i.e., a P-type twin well 112 in an N-type well 111 in a P-type silicon substrate 110.
As an element separation insulating film, a field oxide film 113, for example, is formed above the silicon substrate 110. A silicon oxide film 114, which serves as a gate insulating film, is formed on an element region surrounded by the field oxide film 113. A floating gate electrode 115 is formed on the silicon substrate 114. A control gate electrode (word line) 117 (WL) is formed above the floating gate electrode 115 through a silicon oxide film 116.
An N-type source region 121 and an N-type drain region 122 are formed in the silicon substrate 110 on both sides of the floating gate electrode 115 and the control gate electrode 117. In this case, the source regions (source lines SL's) of all memory cells, for example, are mutually connected.
A silicon oxide film 118 entirely covering memory cells MC's are formed on the memory cells MC's. A contact hole 120 which reaches a drain region 122 is provided in the silicon oxide film 118. A bit line 119 (BL) is formed on the silicon oxide film 118. The bit line 119 contacts with the drain region 122 through the contact hole 120 of the silicon oxide film 118.
Next, description will be given to potentials applied to memory cells in each of the program mode, the read mode and the erase mode of the above-stated NOR-type flash EEPROM.
First, in the program mode, the potential of a selected word line WL is set at, for example, Vpp (e.g., a high potential such as about 10V) and that of an unselected word line WL is set at Vss (e.g., 0V). The potential of a bit line BL to which a memory cell (selected cell), for which “0”-programming is conducted, is connected is set at Vss (e.g., 0V). The potential of a bit lines BL to which a memory cell (unselected cell), for which “1”-programming is conducted, is connected is set at Vss (e.g., 0V). The potential of a source line SL is Vss (e.g., 0V).
At this moment, in the selected cell, the potential of a control gate (word line) is Vpp, that of a drain is Vdp and that of a source is Vss, so that electrons within the source are accelerated and moved to the drain. They become electrons (hot electrons) with high energy in a channel in the vicinity of the drain and are moved into the floating gate by an electric field between the control gate and the channel. Due to this, the threshold voltage of the selected cell increases and “0”-programming is carried out in the cell.
In the unselected cell, on the other hand, the potential of a control gate (word line) is Vpp and those of a drain and a source are Vss, so that no current flows between the drain and the source. Due to this, the threshold voltage of the unselected cell does not increase and “1”-programming is carried out (an erase state is maintained) in the cell.
Next, in the read mode, the potential of the selected word line WL is set at, for example, Vcc (e.g., a potential of about 5V) and that of the unselected word line WL is set at, for example, Vss (e.g., 0V). The bit line BL to which the memory cell (selected cell), for which data read is carried out, is pre-charged with Vd (e.g. a potential of about 1V) and then turned into a floating state. The potential of the bit line BL to which the memory cell (unselected cell), for which no data read is carried out, is set at, for example, Vss (e.g., 0V). The potential of the source line SL is set at, for example, Vss (e.g., 0V).
The threshold voltage of the memory cell (in a “1” state) storing data “1” is lower than Vcc, whereas that of the memory cell (in a “0” state) storing data “0” is higher than Vcc. Due to this, if the potential of the selected word line WL is set at Vcc, the cell in the “1” state is turned on and that in the “0” state is turned off.
Accordingly, a current flows into the cell in the “1” state and the potential of the bit line BL to which this cell is connected is decreased to Vss. No current flows into the cell in the “0” state and the potential of the bit line BL to which this cell is connected, is, therefore, maintained Vd. Data read is executed if a sense amplifier senses the potential change of this bit line BL.
Next, description will be given to potentials applied to memory cells in the erase mode.
Data erase is carried out in units of blocks and simultaneously carried out to all memory cells in each block. A mode for erasing the data of the memory cells in one or a plurality of blocks in a chip is referred to as “a block erase mode” and a mode for erasing the data of the memory cells in all blocks in the chip is referred to as “a chip erase mode”.
In the erase mode, the potentials of all the word lines WL's in the chip are set at, for example, Vss (e.g., 0V). The potentials of the twin wells (i.e., the P-type well and the N-type well) in a selected block are set at, for example, Vee (e.g., a high potential of about 20V) and those of the twin wells in an unselected block are set at, for example, Vss (e.g., 0V). It is noted that the twin wells are provided per block.
At this moment, in each of the memory cells in the selected block, the potential of the control gate (word line) is Vss and those of the twin wells (channel) are Vee, so that a high electric field is applied to the gate oxide film. Due to this, electrons within the floating gate are moved to the twin wells (channel) by an FN tunnel phenomenon. As a result, the threshold voltages of the memory cells in the selected block are decreased and the memory cells are turned into a “1” state (data erase is carried out in the cells).
On the other hand, in each of the memory cells in the unselected block, the potential of the control gate (word line) and those of the twin wells (channel) are set at Vss, so that no high electric field is applied to the gate oxide film. As a result, the memory cells in the unselected block have no change in electron quantity in the floating gate, i.e., no change in threshold voltages and data erase is not, therefore, carried out in the cells.
In the meantime, the NOR-type flash EEPROM has conventionally the following disadvantages in the erase mode.
Memory cells in a block have individual erase characteristics due to manufacturing process or the like. In some cases, the memory cells in the block for which data erase is carried out have individual initial threshold voltages.
These differences in erase characteristics and initial threshold voltage cause the memory cells in the block after block erase is carried out, to have individual threshold voltages and a threshold voltage distribution is formed. Owing to this, when, for example, data erase is completed for all the memory cells in a block, that is, when data erase is completed for the memory cell having the worst erase characteristics in the block (memory cell having the slowest erase speed), the memory cell having the best erase characteristics in the block (memory cell having the fastest erase speed) may turn into an over-erase state.
The over-erase state means that the threshold voltage of a memory cell becomes a negative value. Such an over-erase state of the memory cell causes a significant problem in the read mode. That is to say, in the read mode, the potential of the selected word line WL is set at Vcc (e.g., a potential of about 5V) and that of the unselected word line WL is set at Vss (e.g., 0V) as already described above.
All the memory cells connected to the unselected word lines WL's are turned off, those connected to the selected word line WL are turned on or off according to their states (“1” or “0”) and the potential change of the bit line is detected, thereby carrying out data read.
The unselected memory cell in the over-erase state (which threshold voltage is a negative value) is not turned off but turned on even if a potential of Vss (0V) is applied to the control gate (word line) thereof. Thus, the potentials of the bit line BL to which the unselected memory cell in the over-erase state is connected, is always decreased due to discharge (leak), resulting in a read error, i.e., even if the selected cell is in the “0” state, data “1” is read to the bit line.
To prevent the over-erase of the memory cell, there is known an erase technique which has an erase sequence including not only an erase step but also a pre-program step and a convergence step.
In the pre-program step, the threshold voltages of memory cells, to which data erase is conducted, are made uniform, whereby the probability that memory cells in the over-erase state occur after the erase step is intended to be decreased. In the convergence step, if a memory cell in the over-erase state occurs, then a weak program is carried out to the memory cell, the threshold voltage of the memory cell in the over-erase state is returned to a predetermined voltage and a threshold voltage distribution after the erase step is intended to converge.
Needless to say, in each of the pre-program, erase and convergence operations, a verify operation is performed after each operation to verify whether or not the operation is completely carried out.
Next, a concrete example of the erase sequence will be described.
FIG. 6 shows an example of the erase sequence. It is noted that each of the circuits referred to in the following description is that shown in FIG. 1.
If the command register 19 confirms an erase command and the block of the memory cell array 11 for which an erase operation is executed, the control circuit 21 controls the operations of the respective circuits in the chip so as to execute the erase sequence shown in FIG. 6.
First, after the address counter 16, the timer 25 and the like are reset, a pre-program step is executed for memory cells in a selected block (in steps ST1 to ST2).
The pre-program step is executed according to procedures shown in the sub-routine of FIG. 7.
First, the address Add of the address counter 16 is set at an initial value “0” and the numerical value Cycle of the timer 25 (corresponding to the number of program steps) is set at an initial value “0” (in steps ST41 to ST42). In the potential generating circuit 22, internal power supply for program verify P. V. is set up (in step ST43).
Thereafter, the data of a memory cell selected by the address Add is read (in step ST44). The data of the memory cell (selected cell) selected by the address Add is compared with program data “0” (in step ST45).
That is, it is assumed that a potential (a program verify threshold value) PVT (e.g., 5.5V) which is the lower limit of the threshold values with which it can be determined that a memory cell is in a program state, is a boundary value. If the threshold value of the selected cell is higher than the boundary value, it is determined that the data of the selected cell is “0”. If the threshold value of the selected cell is lower than the boundary value, it is determined that the data of the selected cell is “1”.
If the data of the selected cell does not coincide with the program data “0”, program NG is determined and a data program step (injection of electrons into the floating gate) is executed to the selected cell.
This data program step is repeatedly carried out until the Cycle or the number of program steps reaches a preset number Limit and the data of the selected cell coincides with the program data “0” (in steps ST48 to ST49).
When the Cycle or the number of program steps for the selected cell reaches the preset number Limit, the pre-program step is ended even if the data of the selected cell does not coincide with the program data (in step ST46).
At this moment, a signal ERROR indicating that a program error occurs is set at “1” (in step ST47).
On the other hand, if the data of the selected cell coincides with the program data “0”, program OK is determined and the address Add is advanced by one, whereby the same operation is carried out to a memory cell (selected cell) at the next address. At this moment, the numerical value of the timer 25 is reset at the initial value (in steps ST42 and ST51).
When the data of the selected cell coincides with the program data “0” and the address Add corresponds to the final address in the block, the pre-program step is ended. In that case, the threshold voltage distribution of the memory cells in the selected block is that shown in FIG. 8 (in step ST50).
Next, it is checked whether or not the signal ERROR indicating the presence of a program error is “1”. If a program error occurs, that is, the signal ERROR is “1”, then the erase operation is ended (in step ST3).
If the pre-program is surely executed, that is, the signal ERROR is “0”, an erase step is executed (in step ST4).
The erase step is executed according to procedures shown in the sub-routine of FIG. 9.
First, the address Add of the address counter 16 is set at the initial value “0” and the numerical value Cycle of the timer 25 (corresponding to the number of erase steps) is set at the initial value “0” (in steps ST61 to ST62). In the potential generating circuit 22, internal power supply for the erase verify E. V. is set up (in step ST63).
Thereafter, the data of a memory cell selected by the address Add is read (in step ST64). The data of the memory cell (selected cell) selected by the address Add is compared with an expected value “1” (in step ST65).
That is, it is assumed that a potential (erase verify threshold value) EVT1 (e.g., 3.0V) which is the upper limit of the threshold values with which it can be determined that a memory cell is in an erase state, is a boundary value. If the threshold value of the selected cell is higher than the boundary value, it is determined that the data of the selected cell is “0”. If the threshold value of the selected cell is lower than the boundary value, it is determined that the data of the selected cell is “1”.
If the data of the selected cell does not coincide with the expected value “1”, erase NG is determined and a data erase step (an operation for taking out electrons in the floating gate) is executed to all the memory cells in the selected block.
Here, the data erase step is executed simultaneously to all of the memory cells in the selected block, which operation is peculiar to the flash EEPROM. Thus, the data erase step is executed even to the memory cells other than the selected cell for which data erase has been already completed.
This data erase step is repeatedly carried out until the Cycle or the number of erase steps reaches a preset number Limit and the data of the selected cell coincides with the expected value “1” (in steps ST66, ST68 and ST69).
When the Cycle or the number of program steps for the selected cell reaches the preset number Limit, the erase operation is ended even if the data of the selected cell does not coincide with the expected value “1” (in step ST66).
At this moment, a signal ERROR indicating that an erase step occurs is set at “1” (in step ST67).
On the other hand, if the data of the selected cell coincides with the expected value “1”, erase OK is determined and the address Add is advanced by one, whereby the same operation is carried out to a memory cell (selected cell) at the next address.
At this moment, the numerical value of the timer 25 is not reset at the initial value. This is because the erase operation is carried out to all memory cells (in step ST71).
If the data of the selected cell coincides with the expected value “1” and the address Add corresponds to the final address in the block, then the erase operation is ended. At this moment, the threshold distribution of the memory cells in the selected block is that shown in, for example, FIG. 10 (in step ST70).
Next, it is checked whether or not the signal ERROR indicating the presence or absence of an erase error is “1”. If an erase error occurs, that is, the signal ERROR is “1”, then the erase operation is ended (in step ST5).
If data erase is surely executed, that is, the signal ERROR is “0”, a convergence step is executed (in step ST6).
The convergence step is executed according to procedures shown in the sub-routine of FIG. 11.
First, the address Add (only columns are selected and all row address are unselected) of the address counter 16 is set at the initial value and the numerical value of the timer 25 (corresponding to the number of convergence steps) is set at the initial value “0” (in steps ST81 to ST82). In the potential generating circuit 22, internal power supply for leak check LCK. is set up (in step ST83).
Thereafter, a column leak check (leak check for memory cells in units of columns) is carried out (in step ST84).
The column leak check is to check a leak current flowing through a selected column and to determine whether or not a memory cell in an over-erase state exists while all rows (word lines) are unselected and one column is selected.
Namely, if the total leak current of all the memory cells in the selected column is lower than a reference value, it is determined that the data of the selected column is “0”. If the total leak current of all the memory cells in the selected column is higher than the reference value, it is determined that the data of the selected column is “1”.
Here, the reference value can be replaced by the threshold value of a memory cell. That is, this threshold value is assumed as an over-erase verify threshold value OEVT. The over-erase verify threshold value OEVT is set at, for example, about 0.5V. This setting is made because a leak current occurs to a memory cell having a threshold value lower than 0.5V.
The data of the selected column is compared with an expected value “0” (in step ST85).
If the data of the selected column does not coincide with the expected value “0”, convergence NG is determined and a self convergence step (an operation for eliminating the over-erase state) is executed simultaneously to all of the memory cells in the selected column.
The convergence step can be also referred to as a weak program step. The weak program step means a program operation for setting a potential applied to the control gate (word line) of the selected memory cell low. In the weak program step, the potential of the selected word line is set at, for example, Vpw (e.g., a potential less than 10V).
This convergence step is repeatedly carried out until the Cycle reaches a preset number Limit and the data of the selected column coincides with the expected value “0” (in steps ST86, ST88 and ST89).
Further, when the Cycle or the number of program steps for the selected column reaches the preset number Limit, the convergence step is ended even if the data of the selected column does not coincide with the expected value “0” (in step ST86).
At this moment, a signal ERROR indicating that a convergence has not been completely executed is set at “1” (in step ST87).
On the other hand, if the data of the selected column coincides with the expected value “0”, convergence OK is determined for all the memory cells in the selected column and the address Add is advanced by one, whereby the same operation is carried out to memory cells in the next column (in step ST91).
If the data of the selected column coincides with the expected value “0” and the address Add corresponds to an address for selecting the final column in the block, then the convergence step is ended.
When the convergence step is ended for all columns, the threshold voltage distribution of the memory cells in the selected block is that shown in, for example, FIG. 12 (in step ST90).
Next, it is checked whether or not the signal ERROR indicating that convergence has not been completely executed is “1”. If the signal ERROR is “1”, the erase operation is ended (in step ST7).
If the signal ERROR is “0”, internal power supply for erase verify E. V. is set up in the potential generating circuit 22 (in step ST8).
Thereafter, the data of all memory cells in the selected block are read (in step ST9). The data of all the memory cells are compared with the expected value “1” (in step ST10).
That is, it is assumed that a potential (erase verify threshold value) EVT1 (e.g., 3.0V) which is the upper limit of the threshold values with which it can be determined that a memory cell is in an erase state, is a boundary value. If the threshold value of the selected cell is higher than a boundary value, it is determined that the data of the selected cell is “0”. If the threshold value of the selected cell is lower than the boundary value, it is determined that the data of the selected cell is “1”.
If the data of all the memory cells in the selected block coincide with the expected value “1”, the erase operation is ended.
If the data of all the memory cells in the selected block do not coincide with the expected value “1”, the erase operation is conducted again.
The reason for conducting erase verify after the convergence step is that the upper limit of the threshold voltage distribution of the memory cells may exceed the erase verify threshold value EVT1 again as a result of the convergence step.
Meanwhile, in the NOR-type flash EEPROM, a write (program)/erase test for conducting data program steps and data erase steps repeatedly is executed as a product reliability test.
The sequence of this write/erase test is shown in FIG. 13. Namely, the sequence is the same as the above-stated automatic erase sequence except that the data program steps and data erase steps are repeatedly carried out until the number N of write/erase cycles reaches a maximum number Nmax. That is, the sub-routine of the program step is that shown in FIG. 7, the sub-routine of the erase step is that shown in FIG. 9 and the sub-routine of the convergence step is that shown in FIG. 11.
As stated above, in the conventional NOR-type flash EEPROM, to prevent the occurrence of memory cells in the over-erase state, for example, the erase sequence of the erase operation or that of the write/erase test includes a convergence step.
This convergence step, however, increases time for block erase (or chip erase) conducted to the memory cells.
After data erase, in particular, if the threshold voltage distribution of the memory cells becomes too wide and many memory cells in the over-erase state occur, then it is required to carry out a column leak check and a convergence step (weak program) to almost all bit lines (columns) sequentially and block erase (or chip erase) time thereby becomes very long.
For example, if the erase step for taking out electrons from the floating gate to the channel requires about 100 [ms], the convergence step requires about 1 [s] and the pre-program step executed for all bits requires about 700 [ms], then the erase operation (the pre-program step, the erase step and the convergence step) requires at least about 1.8 [s].
Further, as stated above, a write/erase test for carrying out the program operation and the erase operation repeatedly is conducted as a reliability test in, for example, the flash EEPROM. In this case, the erase operation naturally includes a convergence step.
Consequently, if the program operation and the erase operation are repeatedly carried out, for example, about 1000 times, it takes 1.8 [s]×1000=1800 [s], i.e., 30 minutes per block.
Meanwhile, since test time is proportional to test cost, the longer test time means higher test cost.
If the convergence step is eliminated from the erase operation during the write/erase test, time for one write/erase cycle becomes 0.8 [s] in the above case. Thus, if the program operation and the erase operation are repeatedly carried out about 1000 times, it takes 0.8 [s]×1000=800 [s] per block, making it possible to halve test time compared with that for the operation including the convergence step.
The flash EEPROM having the erase sequence in which the convergence step is executed, requires test time twofold of that for the flash EEPROM having the erase sequence without the convergence step and test cost for the former EEPROM is pushed up accordingly.
These situations become quite serious for, for example, a low-voltage NOR-type flash EEPROM. Namely, if voltage is lowered and a power supply potential Vcc is decreased from, for example, 5V to about 3V, then a potential (read potential) Vcc applied to a selected word line is decreased as well.
The decrease of the read potential Vcc means that the threshold voltage distribution of memory cells after block erase has to fall within a narrow range between Vss (0V) and Vcc.
In this case, as shown in, for example, FIG. 14, an erase verify threshold value EVT1 as a reference for erase verify is lowered. Due to this, if the width of the threshold distribution of the memory cells after block erase remains the same, the lower limit EVTL of the threshold voltage distribution is lowered as well. As a result, the lower limit EVTL becomes far lower than the above-stated over-erase verify threshold value OEVT. In the convergence step, the number of memory cells, to which the weak program for setting the lower limit EVTL higher than the over-erase verify threshold value OEVT is conducted, increases, resulting in longer test time.